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AMD-766 peripheral bus controller revision guide publication # 23615 rev: c issue date: june 2001 tm preliminary information
preliminary information trademarks amd, the amd logo, and combinations thereof, amd athlon, amd-761, amd-762, and AMD-766 are trademarks of advanced micro devices, inc. microsoft is a registered trademarks of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2000-2001 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the amd products described herein may contain design defects or errors (?product errata?) that causes the amd products to deviate from published specifications. currently characterized product errata may be available upon request. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental dam age may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
AMD-766? peripheral bus controller revision guide 23615c?june 2001 preliminary information revision history date rev description april 2001 b initial public release. june 2001 c added errata #22.
2 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information AMD-766? peripheral bus controller revision guide the purpose of the AMD-766? peripheral bus controller revision guide is to communicate updated product information on the AMD-766 ? peripheral bus controller to designers of computer systems and software developers. this guide consists of four major sections: product marking identification: this section, which starts on page 3, provides product types, product revisions, opns (ordering part numbers), and product marking information. product errata: this section, which starts on page 4, provides a detailed description of product errata, including potential effects on system operation and suggested workarounds. an erratum is defined as a deviation from the product ? s specification. a product errata may cause the behavior of the AMD-766 peripheral bus controller to deviate from the published specifications. revision determination: this section starts on page 26. technical and documentation support: this section, which starts on page 27, provides a listing of available technical support resources. it also lists corrections, modifications, and clarifications to listed documents. revision guide policy occasionally, amd identifies deviations from or changes to the specification of the AMD-766 peripheral bus controller. these changes are documented in the AMD-766 ? peripheral bus controller revision guide as errata. descriptions are written to assist system and software designers in using the AMD-766 and corrections to amd ? s documentation on the AMD-766 peripheral bus controller are included. this revision guide documents currently characterized product errata, but is not intended to document all errata that may be found in the controller.
3 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 1 product marking identification product revision family/core AMD-766 package type a = plastic ball grid array c = commercial temperature range case temperature amd-756 tm amd-756ac b date code amd 1998 c AMD-766? AMD-766ac 1999 table 1. valid ordering part number combinations opn package type operating voltage case temperature (max.) AMD-766ac 272-pin pbga 3.0v-3.6v 85 c notes: valid combinations are configurations that are or will be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 2 product errata this section documents AMD-766 peripheral bus controller product errata. the errata are divided into categories to assist referencing particular errata. a unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. table 2 cross-references the revisions of the controller to each erratum. an ? x ? indicates that the erratum applies to the stepping. the absence of an ? x ? indicates that the erratum does not apply to the stepping. shading within the table indicates an addition or modification from the previous release of this document. note: there can be missing errata numbers. errata that have been resolved from early revisions of the controller have been deleted, and errata that have been reconsidered may have been deleted or renumbered. table 2. cross-reference of product revision to errata erratum number and description revision number a0 a1 a2 b0 1 sleep button and power button are not debounced correctly x xx 2 ide ior phy select x xx 3 ide ata-100 specified data hold time not met xxx 4 vdd_rtc draws excessive current xx 5 dma page table not updated for lpc bus xxx 6 dma terminal count status register is set too early xxx 7 bios write lock error xxx 8 pci bus parking while a cycle is taking place xxxx 9 target-driven pci data bus after pci turnaround cycle xxxx 10 pci special cycles being delayed xxxx 11 programmable interval timer does not support unspecified modes xxxx 12 programmable interval timer does not support mode 1 and mode 5 xxxx 13 programmable interval timer does not accept back-to-back writes to the initial count register xxxx 14 programmable interval timer2 does not load correct value into the initial count reg- ister xxxx 15 ide read / write prefetch hangs pci bus xxxx 17 eide controller bus master base address register is 256-byte aligned xxxx 18 usb ohci register specification differences xxxx 19 udma-100 performance does not meet industry-standard benchmarks xxxx 20 usb hccadonehead writeback bug xxxx 21 whql ssid, ssvid non-conformance xxxx 22 multiprocessor system may hang while in full apic mode and ioapic interrupt is masked x
5 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 1 sleep button and power button are not debounced correctly products affected. a0, a1, a2 normal specified operation. whenever the sleep or power button are depressed the corresponding status pm00, bit[slpbtn_sts] or pm00, bit[pwrbtn_sts] should be set. non-conformance. the first sleep button event from a system reset sets pm00, bit[slpbtn_sts]. after this bit is cleared by software, the next sleep button event does not set this bit. the pm00, [pwrbtn_sts] bit behaves in the same fashion. potential effect on system. system will not go to sleep more than once when using sleep button. suggested workaround. reset the system to allow pm00 [slpbtn_sts] and pm00 [pwrbtn_sts] to be set. resolution status. fix planned in b0.
6 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 2 ide ior phy select products affected. a0, a1, a2 normal specified operation. the ide io cell should be connected to the 3-bit phy select signals so that ide data hold times are selectable. non-conformance. the ide io cell was tied to ground instead of the 3-bit phy select signal. this selects the slowest mode and causes probems for udma operations which require fast mode. in a1 stepping a partial fix was implemented to tie the three-bit phy select signal to fast mode. potential effect on system. udma modes will not operate. suggested workaround. use a1 stepping. resolution status. fix planned for b0.
7 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 3 ide ata-100 specified data hold time not met products affected. a0, a1, a2 normal specified operation. ata-100 rev0.6, specifies ultra dma data hold time, t dvhic , at 9ns. non-conformance. the hold time requirement on data from strobe for udma modes 0-4 was increased from 6ns to 9ns in ata-100 rev0.6 specification. AMD-766 peripheral bus controller uses clk100 cycle for all these modes which is inadequate to meet the 9ns hold time requirement. potential effect on system. none detected. suggested workaround. none. resolution status. fix planned for b0.
8 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 4 vdd_rtc draws excessive current products affected. a0, a1 normal specified operation. in moff state the rtc circuit should consume approximately 2 micro-amps of current. non-conformance. AMD-766 peripheral bus controller consumes 2 ma of current in moff state which is 1000 times more than the specified current. potential effect on system. 3.3vdc motherboard batteries will discharge below operating voltage. this will result in cmos settings not being saved. suggested workaround. none. resolution status. fix planned for a2.
9 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 5 dma page table not updated for lpc bus products affected. a0, a1, a2 normal specified operation. dma page table entries need to be updated when switching between dma devices on lpc bus. non-conformance. when a dma channel change occurs the previous dma page table is used. once a first dma transfer is completed after reset, the internal dma page table pointer gets stuck pointing to the initial entry. potential effect on system. cannot use two dma devices back to back. suggested workaround. none. resolution status. fix planned for b0.
10 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 6 dma terminal count status register is set too early products affected. a0, a1, a2 normal specified operation. the ? terminal count reached ? status bit should be set only when the terminal count condition is reached. non-conformance. terminal count status bit for each channel gets set one transfer count early. potential effect on system. none. suggested workaround. none. resolution status. fix planned for b0.
11 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 7 bios write lock error products affected. a0, a1, a2 normal specified operation. when function 0, offset 48 bit [rwr] is set to zero, writes to bios space should not be allowed. non-conformance. when function 0, offset 48 bit [rwr] is set to zero, writes to bios space should not be allowed. however, range ffbe_ffff:ffb0_0 000 at the bottom of the 5mb bios space is not covered by this bit. also this range is not covered by any of the oar locking registers thus this region is always accesible when read. potential effect on system. possible bios security hole. suggested workaround. none. resolution status. fix planned for b0.
12 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 8 pci bus parking while a cycle is taking place products affected. a0, a1, a2, b0 normal specified operation. the AMD-766 peripheral bus controller must not drive pci c/be# lines while entering pci bus park mode. non-conformance. if the northbridge parks the pci bus on the AMD-766 peripheral bus controller while the northbridge is executing a pci cycle, the AMD-766 will drive the c/be# lines for one pci clock. potential effect on system. none. the amd northbridge should always park on itself (default). suggested workaround. none. resolution status. no fix planned.
13 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 9 target-driven pci data bus after pci turnaround cycle products affected. a0, a1, a2, b0 normal specified operation. the target of a pci read cycle drives the pci data bus after the turnaround cycle has completed. this is to limit the amount of time that the pci address and data bus floats. non-conformance. when the AMD-766 peripheral bus controller is a target for a pci read cycle, the AMD-766 does not drive the pci data bus until it is ready to supply the data. potential effect on system. none. suggested workaround. none. resolution status. no fix planned.
14 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 10 pci special cycles being delayed products affected. a0, a1, a2, b0 normal specified operation. whenever a pci special cycle is directed to the AMD-766 peripheral bus con- troller, the data phase can be delayed by 16 pci clocks after assertion of frame# control signal. non-conformance. when a pci special cycle is directed to the AMD-766 peripheral bus controller the data phase must be valid by the third pci clock after the assertion of frame# control signal. if the pci data is delayed longer than three pci clocks past assertion of frame#, the AMD-766 peripheral bus controller will respond improperly. potential effect on system. none. the amd-761 ? system controller (northbridge) always presents valid data for pci special cycle two pci clocks after assertion of frame#. suggested workaround. none. resolution status. no fix planned.
15 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 11 programmable interval timer does not support unspecified modes products affected. a0, a1, a2, b0 normal specified operation. the programmable interval timer (p.i.t.) in the AMD-766 controller only accepts specified modes of 0 through 5 as documented in industry-standard 82c54 documentation. non-conformance. some commercially available diagnostic programs such as wincheckit98 may improp- erly program the timer for unspecified modes 6 or 7. other existing southbridge devices tolerate these unspecified modes and default to a known mode of operation. potential effect on system. if the AMD-766 controller p.i.t. is programmed to an unspecified mode such as mode 6 or mode 7 the system will hang. suggested workaround. do not program the AMD-766 controller p.i.t. to unspecified modes. resolution status. no fix planned.
16 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 12 programmable interval timer does not support mode 1 and mode 5 products affected. a0, a1, a2, b0 normal specified operation. the programmable interval timer (p.i.t.) in the AMD-766 controller should accept specified modes of 0 through 5 as documented in industry-standard 82c54 documentation. non-conformance. the AMD-766 controller p.i.t. was designed not to support the specified external gate0, gate1, and gate2 signals. this lack of external access makes p.i.t. modes 1 and 5 unusable. potential effect on system. none. suggested workaround. do not program the AMD-766 controller p.i.t. to mode 1 or mode 5. resolution status. no fix planned.
17 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 13 programmable interval timer does not accept back-to-back writes to the initial count register products affected. a0, a1, a2, b0 normal specified operation. the programmable interval timer (p.i.t.) in the AMD-766 controller should latch all writes to the initial count register cr for mode 2 as documented in industry-standard 82c54 documentation. non-conformance. the AMD-766 controller p.i.t. initial count register does not correctly latch a new ini- tial count value before the previously loaded terminal count has been reached. if only the initial count register cr is written this new value will not be latched. potential effect on system. none. suggested workaround. write a complete control word to the control word register located at port 43h. then write a new initial count value "cr" for the selected counter to port 40h or port 41h or port 42h. this process will cause the counters to be loaded immediately with correct count values.. resolution status. no fix planned.
18 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 14 programmable interval timer2 does not load correct value into the initial count register products affected. a0, a1, a2, b0 normal specified operation. the programmable interval timer (p.i.t.) in the AMD-766 controller should latch all writes to the initial count register for mode 0 as documented in industry-standard 82c54 doc- umentation. non-conformance. the AMD-766 controller p.i.t. timer2 initial count register does not correctly latch a new initial count value when the following sequence is used: step 1 disable timer2 by writing to port61[tmr2en]. step 2 program timer2 into mode 0 and as 16-bit binary count. step 3 program the initial count register cr as 0100h. step 4 re-enable timer2 by writing to port61[tmr2en]. the AMD-766 p.i.t. counter will only latch the lower 8 bits of the initial count value. for example if cr is loaded with count 0100h then the value of ff00h is loaded into initial count register cr. this errata only exists in timer2. potential effect on system. none. suggested workaround. none. resolution status. no fix planned.
19 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 15 ide read / write prefetch hangs pci bus products affected. a0, a1, a2, b0 normal specified operation. when ide read / write prefetch is enabled and the ide transfer mode is pio the AMD-766 ide controller should transfer ide data to the pci bus. non-conformance. if an ide transfer in udma mode occurs before a pio prefetch transfer, the pio trans- fer mode disk drive data will not be transferred from the ide bus to the pci bus. potential effect on system. the AMD-766 ide controller causes pci bus retry cycles to occur forever. the system may hang or not boot to the operating system. suggested workaround. do not enable ide read / write prefetch in bios setup. the current bios setup default for ide read / write prefetch is disabled. resolution status. no fix planned.
20 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 17 eide controller bus master base address register is 256-byte aligned products affected. a0, a1, a2, b0 normal specified operation. the ide controller function in the AMD-766 peripheral bus controller con- tains a pci configuration space offset at c1a20 "eide controller bus master control registers base address." these bits specify a 16-byte i/o address that maps to an eide register set (ibmx) that is compliant with the sff 8038i rev 1.0 specification "bus master programming interface for ide ata controllers." non-conformance. the ide controller function in the AMD-766 peripheral bus controller has imple- mented a 256-byte i/o address alignment instead of the 16-byte i/o address alignment. potential effect on system. none. all known software supports 16-byte and 256-byte i/o address bound- aries. suggested workaround. none. resolution status. no fix planned.
21 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 18 usb ohci register specification differences products affected. a0, a1, a2, b0 normal specified operation. the usb function in the AMD-766 peripheral bus controller was designed according to the open host controller interface specification for usb (open hci), release 1.0a. the open hci specifies the following internal registers : hcdonehead is specified as read-only. hcfmnumber is specified as read-only. hfminterval bit 30 is specified in this register as part of the fsmps field. hcestatus the cmddata bit is specified as read/write. hcecontrol the gatea20sequence bit is specified as read/write. non-conformance. the usb function in the AMD-766 peripheral bus controller has implemented the above usb registers as follows: hcdonehead is implemented as read/write. hcfmnumber is implemented as read/write. hfminterval bit 30 is not implemented, always returns zero. hcestatus the cmddata bit is implemented as read-only. hcecontrol the gatea20sequence bit is implemented as read-only. potential effect on system. none. suggested workaround. none. resolution status. no fix planned.
22 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 19 udma-100 performance does not meet industry-standard benchmarks products affected. a0, a1, a2, b0 normal specified operation. when the ide controller is programmed for udma-100 mode, the expected data transfer rate is 100 mbytes per second (mbps). non-conformance. if the ide controller is programmed for udma-100 mode, the observed data transfer rate is on the order of 78 mbps. potential effect on system. no functional failures occur. this errata only affects ide udma-100 perfor- mance. suggested workaround. none. resolution status. no fix planned.
23 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 20 usb hccadonehead writeback bug products affected. a0, a1, a2, b0 normal specified operation. at each start of frame a write to the hcca memory space is initiated to update the frame number. if a td was retired the donehead pointer is also written to hcca. once the donehead is written back, no writebacks to the donehead in hcca are allowed until the donehead interrupt status bit is cleared. non-conformance. the issue arises when an sof writeback is pending and the donehead interrupt status is cleared with additional td retired requiring another donehead writeback. the list processor updates its current writeback request transfer size to include the next donehead pointer, but the bus master only accepts the size of the original request. the result is the list processor thinks the done- head was written back and clears the pointer, but the bus master did not complete the transfer and the pointer is lost. microsoft is aware of the problem and is evaluating a software patch to the driver. potential effect on system. none have been observed. in the worst case, a transfer does not fully complete if the above criteria occurs. the above criteria must occur within a one-pclk window for this to be observed. suggested workaround. none. most commercially available ohci usb controller products do not imple- ment this fix. no observations have ever occurred in validation testing or usb plugfests. resolution status. no fix planned.
24 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 21 whql ssid, ssvid non-conformance products affected. a0, a1, a2, b0 normal specified operation. subsystem registers in the pci header are located at offset 2ch ? 2dh (sub- system vendor id ? ssvid), and 2eh ? 2fh (subsystem id ? ssid). pc99 requires that these registers exist for all non-bridge function spaces. these registers are required to be read-only. non-conformance. the AMD-766 peripheral bus controller did not implement these registers for the non- bridge function spaces within the device (i.e. the ide, usb, and system management function spaces). potential effect on system. fails whql testing. no other system effects. suggested workaround. none needed. most commercially available southbridge products do not implement these registers. resolution status. no fix planned.
25 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 22 multiprocessor system may hang while in full apic mode and ioapic interrupt is masked products affected. b0 normal specified operation. the AMD-766 peripheral bus controller is designed to support full apic mode in multiprocessor systems for system management events. if an interrupt is masked in the amd- 766 apic controller then the corresponding interrupt message should not be sent to the processor via the 3- wire apic bus. non-conformance. the AMD-766 peripheral bus controller will send a interrupt message via the 3-wire apic bus regardless if the interrupt is masked or not. potential effect on system. since the processor had previously masked the apic interrupt it is not expecting to receive future apic messages for the masked interrupt. the apic controller will continuously send the interrupt message via the 3-wire bus until a processor accepts the message, causing the system to hang. a system hang has been observed when executing a server shutdown command in novell netware versions 5.0 or 5.1 while using a serial mouse. during the server shutdown sequence, software writes an invalid cpu id to the ioapic redirection table and the system does not complete the shutdown. note: no failure has been observed when using a ps/2 mouse. suggested workaround. none. resolution status. no fix planned.
26 AMD-766 ? peripheral bus controller revision guide 23615c ? june 2001 preliminary information 3 revision determination table 3 summarizes the AMD-766 ? peripheral bus controller pci revision id register for function 0 at offset 8 to determine the version of silicon. table 3. AMD-766? peripheral bus controller revision ids sequence revision function 0h offset 8h 1 a0 01h 2 a1 01h 3 a2 01h 4 b0 02h 5 reserved 03h 6 reserved 04h
27 23615c ? june 2001 AMD-766 ? peripheral bus controller revision guide preliminary information 4 technical and documentation support 4.1 documentation support the following documents provide additional information regarding the operation of the AMD-766 peripheral bus controller: amd-761 ? system controller data sheet , order# 24088 amd-762 ? system controller data sheet , order# 24416 AMD-766 ? peripheral bus controller data sheet , order# 23167 amd athlon ? system bus specification , order# 21902 amd athlon ? processor bios, software, and debug tools developers guide , order# 21656 amd athlon ? processor model 4 data sheet , order# 23792 amd athlon ? mp processor model 6 data sheet , order# 24685 for the latest updates, refer to www.amd.com and download the appropriate files. for documents under nda, please contact your local sales representative for updates.

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